Verilog | D Flip-Flop

by Online Tutorials Library July 14, 2022

D Flip-Flop

A D flip-flop is a sequential element that follows the input pin d at the clock’s given edge. D flip-flop is a fundamental component in digital logic circuits.

There are two types of D Flip-Flops being implemented: Rising-Edge D Flip Flop and Falling-Edge D Flip Flop.

D flip flop is an edge-triggered memory device that transfers a signal’s value on its D input to its Q output when an active edge transition occurs on its clock input. Then, the output value is held until the next active clock cycle.

Flip flops are inferred using the edge triggered always statements. The always statement is edge-triggered by including either a posedge or negedge clause in the event list. Here are some examples of sequential always statements, such as:

  always @(posedge Clock)  always @(negedge Clock)  always @(posedge Clock or posedge Reset)  always @(posedge Clock or negedge Reset)  always @(negedge Clock or posedge Reset)  always @(negedge Clock or negedge Reset)  

If an asynchronously reset flip flop is being modeled, a second posedge or negedge clause is needed in the event list of the always statement. Also, most synthesis tools require that the reset must be used in if statement directly following the always statement, or after begin if it is in a sequential begin-end block.

Example

  //Active low asynchronous reset         always @(posedge Clock or negedge Reset)         begin              if (!Reset)              …….              ……..  end  

Design 1: With the async active-low reset

  module dff (input d,                input rstn,                input clk,                output reg q);    always @ (posedge clk or negedge rstn)         if (!rstn)            q <= 0;         else            q <= d;  endmodule  

Hardware Schematic

Testbench

  module tb_dff;  reg clk;  reg d;  reg rstn;  reg [2:0] delay;        dff  dff0 ( .d(d),                  .rsnt (rstn),                  .clk (clk),                  .q (q));        // Generate clock      always #10 clk = ~clk;        // Testcase      initial begin      clk <= 0;      d <= 0;      rstn <= 0;        #15 d <= 1;      #10 rstn <= 1;      for (int i = 0; i < 5; i=i+1) begin      delay = $random;      #(delay) d <= i;      end      end  endmodule  

Design 2: With sync active-low reset

  module dff (input d,                input rstn,                input clk,                output reg q);    always @ (posedge clk)         if (!rstn)            q <= 0;         else            q <= d;  endmodule  

Hardware Schematic

Testbench

  module tb_dff;  reg clk;  reg d;  reg rstn;  reg [2:0] delay;        dff  dff0 ( .d(d),                  .rsnt (rstn),                  .clk (clk),                  .q (q));        // Generate clock      always #10 clk = ~clk;        // Testcase      initial begin      clk <= 0;      d <= 0;      rstn <= 0;        #15 d <= 1;      #10 rstn <= 1;      for (int i = 0; i < 5; i=i+1) begin      delay = $random;      #(delay) d <= i;      end      end  endmodule  

Next TopicT Flip Flop

Verilog | D Flip-Flop

D Flip-Flop

Design 1: With the async active-low reset

Design 2: With sync active-low reset

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