behavioral modelling and timing

Verilog Multiplexer A multiplexer is a device that selects one output from multiple inputs. It is also known as a data selector.…

Gate Level Modeling In Verilog, most of the digital designs are done at a higher level of abstraction like RTL. However, it…

Verilog Scalar and Vector Verilog needs to represent individual bits as well as groups of bits. A single bit sequential element is…

Verilog Gray Counter Gray code is a kind of binary number system where only one bit will change at a time. Today…

Verilog Scheduling Semantics Verilog design and testbench typically have many code lines comprising of always or initial blocks, continuous assignments, and other…

Verilog Initial Block The always block indicates a free-running process, but the initial block indicates a process executes exactly once. Both constructs…

Verilog Simulation Basics Verilog is a hardware description language, and there is no requirement for designers to simulate their RTL designs for…

Verilog Inter and Intra Delay Verilog delay statements can have delays specified either on the left-hand side of the assignment operator’s right-hand…

Switch Level Modeling The switch level of modeling provides a level of abstraction between the logic and analog-transistor levels of abstraction. It…

JK Flip Flop The JK flip-flop is the most versatile of the basic flip flops. A JK flip-flop is used in clocked…